Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: October 23, 2019
Version Found: v18.0
Bug ID: 2205931877
IP: Avalon-MM Stratix 10 Hard IP for PCI Express, Avalon-ST Stratix 10 Hard IP for PCI Express

Why does the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer get stuck in reset when Function-Level Reset FLR is initiated?

Description

When Function-Level Reset (FLR) capability is disabled, a Configuration Write setting the Device Control Register's parameter Initiate Function-Level Reset to 1 will cause the Intel® Stratix® 10 L/H-Tile PCIe* Endpoint's Transaction Layer to be stuck in reset.

The Intel® Stratix® 10 L/H-Tile PCIe* Endpoint will respond to subsequent requests with Unsupported Request (UR) TLP.

Conventional reset is needed to recover from this error case, e.g. PERST#, Hot Reset or Link Disable/Enable.

Workaround/Fix

To work around this problem, enable FLR capability in the IP Parameter Editor.

 

The FLR capability has been enabled by default starting with the Intel® Quartus® Prime Pro edition software version 19.3.