Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property

Last Modified: November 06, 2019
Version Found: v18.0
Bug ID: 2205691060
IP: Avalon-MM Stratix 10 Hard IP for PCI Express

Why does the Intel® Stratix® 10 Avalon® -MM Interface for PCIe* IP with internal DMA send out the read mover "Done" status before it completes the data transfer?


This problem is due to a datapath race condition. The DMA read mover "Done" status update and the completion data are split internally to two (2) different paths/buffers. Data takes a longer path to the Avalon® -MM slave compared to the status update.



This datapath race condition is easily observed in simulation. However, the read mover "Done" status reported a few clock cycles earlier than the data transfer completion will not be a problem in real hardware system due to latency.