Due to a problem with the Intel® Quartus® Prime Pro Edition version 19.1 software, the 25G Ethernet Intel® FPGA IP with ready latency set to 3 will transmit incorrect traffic when either the TX start of packet (SOP) or end of packet (EOP) signals are asserted on the same cycle as the valid signal was de-asserted.
Device Family: Intel® Arria® 10, Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Type: Answers, Errata
Area: Intellectual Property
Last Modified: July 08, 2019
Version Found: v19.1
Bug ID: 1507258191