Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Version Found: v18.1 Update 1
Bug ID: 2007758041

Why does my multichannel 10/25G variant with PTP enabled and the “PTP Channel Placement Restriction” of “EHIP1/3” of the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP fail in the fitter?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.1.1 and earlier, a multichannel 10/25G variant with PTP enabled and the  “PTP Channel Placement Restiction” of “EHIP1/3” for multichannel variants of the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP will fail in the fitter. The fitter error will take the following form:

 

Error(15744): In atom 'av_top|alt_ehipc3_0|alt_ehipc3_hard_inst|EHIP_CORE.c3_ehip_core_inst' 

The settings must match one or more of these conditions:

( topology != ELANE_1CH_PTP ) OR ( topology != ELANE_1CH_PTP ) 

But the following assignments violate the above conditions: 

topology = ELANE_1CH_PTP 

In atom 'av_top|alt_ehipc3_0|alt_ehipc3_hard_inst|SL_NPHY.altera_xcvr_native_inst|alt_ehipc3_nphy_elane|g_xcvr_native_insts[0].ct3_xcvr_native_inst|inst_ct3_xcvr_channel|inst_ct3_hssi_ehip_lane' 

Error(15744): The settings must match one or more of these conditions:  

( topology != ELANE_1CH_PTP ) OR ( topology != ELANE_1CH_PTP ) 

But the following assignments violate the above conditions:  

topology = ELANE_1CH_PTP

Workaround/Fix

To workaround this problem, choose the “PTP Channel Placement Restriction” of “EHIP0/2” option in the GUI and alter the pinout of the device accordingly.

 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.