Device Family: Intel® Stratix® 10 DX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: October 23, 2019
Version Found: v19.3
Bug ID: 14010045894

Why does my Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* show lower read performance in Intel® Quartus® Prime Pro version 19.3?

Description

The Intel® FPGA P-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express* currently supports up to 64 outstanding requests with a Max Read request size of 512 Bytes. If the round trip latency (Time from Memory Read to Completion) is greater than 1.5 us, the number of outstanding requests may not be enough to saturate the Read throughput.

Workaround/Fix

 

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.