Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: December 18, 2019
Version Found: v19.3
Version Fixed: v19.4
Bug ID: 1507412456
IP: Avalon-ST Stratix 10 Hard IP for PCI Express

Why does Intel® Stratix ® 10 Avalon®-ST Interface for PCI Express* IP show BAR size of 7 bits is supported?

Description

Due to incorrect rule check in the IP GUI, Intel® Stratix ® 10 Avalon®-ST Interface for PCI Express* IP for Intel® Quartus® Prime Pro 19.3 and
earlier allows minimum BAR size of 7 bits to be selected. However, this selection will still show FPGA advertising 8 bits of BAR size.

The minimum BAR size supported is 8 bits. 

Workaround/Fix

This problem is fixed in Intel® Quartus® Prime Pro software version 19.4.