Due to a problem in the Intel® Quartus® Prime Pro Edition software version 19.3, when Intel® P-Tile/H-Tile Avalon® Memory Mapped (Avalon-MM) IP for PCI Express is configured with multiple BARs of different size, BAM upper address is not correctly masked according to the BAR size. If the system does not align BARs physical address to the highest BAR size, the address field on the user side size will be incorrect.
For example for BAR0: 64KB and BAR2: 1MB, system assigns the following physical address:
F021000 for BAR0
F020000 for BAR2
BAM address is 20 bits
When system issues a write or read request targeting BAR0 offset 0x800, BAM interface will output address 0x10800 instead of 0x00800