Device Family: Intel® Arria® 10

Type: Answers, Errata

Area: Intellectual Property

Last Modified: June 19, 2019
Version Found: v16.1
Bug ID: 1507196811
IP: Arria 10 Hard IP for PCI Express

Why does the Intel® Arria® 10 Hard IP for PCI* Express signal tx_out periodically transition to high impedance in simulation at LTSSM = Recovery Speed state?


When the LTSSM is in Recovery Speed state, the Intel® Arria® 10 Hard IP for PCI* Express will send out Electrical Idle Ordered Sets (EIOS) before transitioning to electrical idle. This behavior is represented in simulation by tx_out signal periodically transitioning to high impedance.  Therefore, if a third-party Bus Functionality Model (BFM) used for simulation interprets the high impedance as unknown symbols, this will cause the bit sequence to be corrupted and LTSSM transitioning between Recovery Speed and Recovery Lock state.


Simulations using Intel® BFM and Avery* BFM are not affected by this behavior.

If using third party BFM for simulation, please ensure tx_out transitioning to high impedance is not interpreted as unknown symbol.