Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property

Last Modified: January 03, 2019
Version Found: v17.0
Bug ID: FB: 1507000479;

Why do I see errors related to an invalid reference clock frequency when generating the JESD204B IP Design Example in Intel® Quartus® Prime Pro software version 17.0 and later?


When targeting the Intel® Arria® 10, Intel® Cyclone® 10 GX or Intel® Stratix® 10, devices, the JESD204B IP design example components (IOPLL/Core PLL and ATX PLL) share the same reference clock frequency with the CDR reference clock.

You may see errors in the Intel® Quartus® Prime Pro software version 17.0 or later during JESD204B IP design example generation or compilation. This is due to the selected reference clock frequency not being valid for other design example components.

Below are examples of error messages that may be seen :

Error: altjesd_ed_qsys_RX_TX_xcvr_atx_pll_0.xcvr_atx_pll_0: "N counter" (atx_pll_ref_clk_div) 0 is out of range: 1-2, 4, 8

Error: altjesd_ed_qsys_RX_TX_xcvr_atx_pll_0.xcvr_atx_pll_0: "PLL auto mode reference clock frequency (Integer)" (set_auto_reference_clock_frequency) 34.5 is out of range

Error: qsys-generate failed with exit code 3

Error: altjesd_ed_qsys_RX_TX_core_pll.core_pll: Failed to compute output counter 0 frequency dropdown values: Failed to retrieve freq list.

Error: altjesd_ed_qsys_RX_TX_core_pll.core_pll: Reference clock frequency 780.878049 is out of legal range (10.0:750.0)

Error: altjesd_ed_qsys_RX_TX_core_pll.core_pll: "Reference Clock Frequency" (gui_reference_clock_frequency) 780.878049 is out of range: 10.0-750.0


To work around this problem, choose another reference clock frequency from the PLL/CDR Reference Clock Frequency drop-down list in the JESD204B IP Parameter Editor, and regenerate the design example.

This is problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro software.