Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: January 28, 2019
Version Found: v18.0
Bug ID: HSD-ES 1507001186

Why does the Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI* Express IP's dynamically  generated example design fail timing on Intel® Stratix® 10 ES1 and ES2 devices?

Description

Due to a problem with the Intel® Quartus® Prime Pro version 18.0 and 18.1, the Avalon-MM Intel® Stratix® 10 Hard IP+ for PCI Express IP's dynamic generated example design fails static timing analysis.

Workaround/Fix

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.