Why does the AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 FPGA fail to retransmit Ethernet packets in Avalon® Streaming (Avalon-ST) reverse loopback at 10 Mbps and 100 Mbps ?

Description

Due to a problem with the AN 830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design for Intel® Stratix® 10 FPGA, the reference design sets the ETH_SPEED bit (Ethernet speed control) in the command register of the Triple-Speed Ethernet Intel® FPGA IP core to 1 through the config.tcl script.

When the ETH_SPEED setting is set to 1,

if the link speed is 1000 Mbps, the Triple-Speed Ethernet Intel® FPGA IP RX channel outputs Ethernet packets to the Avalon®-ST interface
if the link speed is either 10 Mbps or 100 Mbps, no Ethernet packets output to the Avalon-ST interface.

Workaround/Fix

To work around this problem, change the ETH_SPEED setting in config.tcl file of the reference design to 0. Look for below code in config.tcl and modify as per example below.

set ETH_SPEED 0; # 10/100Mbps = 0 & 1000Mbps = 1

This problem is scheduled to be fixed in a future release of the AN 830 reference design.

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