Due to a problem in AN830: Intel® FPGA Triple-Speed Ethernet and On-Board PHY Chip Reference Design that was generated using Intel® Quartus® Prime Pro Edition version 17.1 software, Intel® FPGA Triple-Speed Ethernet IP core fails to perform auto-negotiation with link partner at 10Mbps and 100Mbps.
This is because Intel® Stratix® 10 GX Signal Integrity Development Kit Board on-board Marvell* 88E1111 PHY chip is not configured to advertise 10Mbps and 100Mbps speed correctly during the auto-negotiation with the link partner.