Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property

Last Modified: June 10, 2019
Version Found: v18.1
Bug ID: 2007758264
IP: 25G Ethernet

Why does ModelSim* simulator stop unexpectedly when simulating the 25G Ethernet Intel® FPGA IP Design Example with "enable 10G/25G dynamic rate switching"?


Due to a problem with the 25G Ethernet Intel® FPGA IP in Intel Quartus® Prime Pro edition version 18.1, the design example with "enable 10G/25G dynamic rate switching"  selected may stop unexpectedly in the ModelSim* simulator.  

The ModelSim transcript stops at the simulation stages below:

  • # Switching to 25G mode : 25G Reconfig start
  • # Switching to 25G mode : 25G Reconfig End
  • #Waiting for RX alignment  



To work around this problem, modify of the example design in the following directory

  • alt_e25s10_0_example_design\example_testbench\

In, find "elab" and replace with "elab_debug"

  • elab to elab_debug

This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro software.