Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: Mon Mar 18 2019 16:00:00 GMT-0700
Version Found: v18.0
Bug ID: 1408936902
IP: Altera Temperature Sensor

Why is the signal cmd_ready of the Temperature Sensor Intel® Stratix® 10 FPGA IP at high impedance state in simulation?

Description

The Temperature Sensor Intel® Stratix® 10 FPGA IP simulation model is not fully featured in the Intel® Quartus® Prime Pro Edition software. The output signal cmd_ready is at high impedance state (cmd_ready = 'bz) .

Workaround/Fix

The Temperature Sensor Intel® Stratix® 10 FPGA IP simulation model is scheduled to be updated in a future release of the Intel® Quartus® Prime Pro Edition software.