Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Answers

Area: Intellectual Property


Last Modified: July 03, 2019
Version Found: v19.1
Bug ID: 1507180758, 1507182300
IP: JESD204B

Why do I see a disparity error in my JESD204B receiver device, when using the JESD204B Intel® FPGA IP in TX mode in Intel® Stratix® 10 devices with E-Tile transceivers?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.1 software, when using the JESD204B Intel® FPGA IP in TX mode in Intel® Stratix® 10 devices with E-Tile transceivers, the IP will introduce a disparity error when configured for a single lane ( L=1) in bonded mode.

Workaround/Fix

To work around this problem, when configuring the JESD204B Intel® FPGA IP IP in L=1 mode, enable non-bonded mode. 

This problem is planned to be fixed in a future release of the Intel® Quartus® Prime Pro Edition Software.