Device Family: Intel® Arria® 10, Arria® V, Cyclone® V, Intel® Stratix® 10, Stratix® V

Intel Software: Quartus Prime

Type: Answers

Area: Intellectual Property


Last Modified: June 10, 2019
Version Found: v17.1
Version Fixed: v19.1
Bug ID: 2205697652
IP: CPRI

Why does the CPRI v6.0 Intel® FPGA IP generate multiple start-of-packet words on the GMII RX Output?

Description

Due to a problem with the CPRI v6.0 Intel® FPGA IP core in the Intel® Quartus® Prime software v17.1, you may observe multiple initial start-of-packet on the GMII RX output if there are idle cycles in the gmii_rxdv within a packet. 

Workaround/Fix

No workaround for this problem exists.

This problem has been fixed in Intel® Quartus® Prime Edition software version 19.1.