Device Family: Intel® Arria® 10, Arria® II, Arria® V, Intel® Cyclone® 10 LP, Cyclone® IV, Cyclone® V, Stratix® IV, Stratix® V

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: DSP, Intellectual Property

Last Modified: December 18, 2019
Version Found: v17.0
Bug ID: 1507360943
IP: Clocked Video Input II (4K Ready)

Why are the stable and resolution valid bits within the Status register of the Clocked Video Input II Intel® FPGA IP stuck at 0?


Due to a problem with the Clocked Video Input II (4K Ready) Intel® FPGA IP in Intel® Quartus® Prime version 17.0 software, you may observe the above problem if you are using embedded synchronization mode.


There is no workaround for this problem. This problem will be fixed in a future version of the Intel® Quartus® Prime software.