Article ID: 000080664 Content Type: Troubleshooting Last Reviewed: 03/16/2021

Why are the out_valid and out_data of the CIC Intel® FPGA IP stuck at 0 when the "Number of stages" parameter is of a power of 2?

Environment

  • Intel® Quartus® Prime Standard Edition
  • Intel® Quartus® Prime Pro Edition
  • CIC Intel® FPGA IP
  • BUILT IN - ARTICLE INTRO SECOND COMPONENT
    Description

    Due to a problem with the CIC Intel® FPGA IP in Intel® Quartus® Prime version 18.1 software, you may observe the above problem if the value of "Number of stages" is of power of 2 and the "Filter type" is Interpolator.

    Resolution

    There is no workaround for this problem. This problem will be fixed in a future version of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 10 products

    Cyclone® IV FPGAs
    Stratix® V FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs
    Cyclone® V FPGAs and SoC FPGAs
    Intel® Cyclone® 10 FPGAs
    Intel® Arria® 10 FPGAs and SoC FPGAs
    Arria® V FPGAs and SoC FPGAs
    Stratix® IV FPGAs
    Arria® II FPGAs
    Intel® MAX® 10 FPGAs