Device Family: Intel® Arria® 10, Arria® II, Arria® V, Intel® Cyclone® 10, Cyclone® IV, Cyclone® V, Intel® MAX® 10, Intel® Stratix® 10, Stratix® IV, Stratix® V

Intel Software: Quartus Prime Pro, Quartus Prime Standard

Type: Answers

Area: DSP, Intellectual Property

Last Modified: November 06, 2019
Version Found: v18.1
Bug ID: 1507322692, 1409080675

Why are the out_valid and out_data of the CIC Intel® FPGA IP stuck at 0 when the "Number of stages" parameter is of a power of 2?


Due to a problem with the CIC Intel® FPGA IP in Intel® Quartus® Prime version 18.1 software, you may observe the above problem if the value of "Number of stages" is of power of 2 and the "Filter type" is Interpolator.


There is no workaround for this problem. This problem will be fixed in a future version of the Intel® Quartus® Prime software.