Device Family: Intel® Stratix® 10 GX

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property

Last Modified: November 11, 2019
Version Found: v18.1
Version Fixed: v19.3
Bug ID: 1507313024
IP: 25G Ethernet

Why does the 25G Ethernet Intel® FPGA IP interface not work correctly if two independent 25G Ethernet Intel® FPGA IPs with different parameters are instantiated in one Intel® Stratix® 10 FPGA design?


Due to a problem in the Intel® Quartus® Prime Pro Edition version 18.1 or earlier, when you instantiate two "25G Ethernet Intel® FPGA IPs" with different parameters in one Intel® Stratix®10 FPGA design you will see one 25G Ethernet interface will not work as expected.

If different parameters or features are enabled in one instance of the IP, but disabled in the other problems can be observed. This is because some source files generated by the IP have the same module name but different parameters, thus the software will overwrite the same module if they are implemented in one design. This results in abnormal behaviour for one of the 25G Ethernet interfaces.


This problem is fixed beginning with the Intel® Quartus® Prime Pro edition software version 19.3.