Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX

Type: Answers, How-To

Area: Intellectual Property

Last Modified: June 24, 2019
Version Found: v17.1
Bug ID: 1507165133
IP: Arria 10 Hard IP for PCI Express

Why do I get error "Unknown uid = xhip_block_1_1" when executing the a10_disableiei.tcl script to disable electrical idle inference for the Intel® Arria® 10 and Intel® Cyclone® 10 GX PCI-SIG Compliance Base Board (CBB) design?


The a10_disableiei.tcl script disables electrical idle inference for all 4 PCIe* Hard IPs of the Intel® Arria® 10.  Therefore, for Intel® Arria® 10 and Intel® Cyclone® 10 GX that have less than 4 PCIe* Hard IPs, executing the script will return this error.

Internal Error: Sub-system: ASM2, File: /quartus/comp/asm2/asm2_state.cpp, Line: 1469

Unknown uid = xhip_block_1_1


To work around this problem, comment out the unavailble PCIe* Hard IPs in the a10_disableiei.tcl script.

For example,  the 10AX115N1F40I1LP device uses only has 2 PCIe* Hard IPs not 4. Therefore, the 2 unavailable Hard IPs, xhip_block_1_1 and xhip_block_3_1, should be commented out. 

xhip_block_1_0 = Bottom Left Location

xhip_block_1_1 = Top Left Location

xhip_block_3_0 = Bottom Right Location

xhip_block_3_1 = Top Right Location