Device Family: Intel® Agilex™, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Answers, Errata

Area: Intellectual Property


Last Modified: July 08, 2019
Version Found: v19.1
Version Fixed: v19.2
Bug ID: 1507229498

When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP core variant with PTP enabled, why does the Intel® Quartus® Prime Pro fitter fail if using the EHIP 1/3 IEEE1588/PTP channel placement restriction?

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition version 19.1 software,  the E-tile Hard IP for Ethernet Intel® FPGA IP in 100GE or 1 to 4 10GE/25GE with optional RSFEC and 1588 PTP core variant with PTP enabled cannot pass fitter compilation if using EHIP 1/3 as the channel placement restriction.

Workaround/Fix

To work around this error, use EHIP 0/2 instead of EHIP 1/3 as the channel placement restriction.

This problem has been fixed starting in v19.2 of the Intel® Quartus® Prime Pro Edition software.