Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10 GX, Cyclone® V, Intel® Stratix® 10, Stratix® V

Intel Software: Quartus Prime

Type: Answers

Area: Intellectual Property


Last Modified: June 19, 2019
Version Found: v17.0
Bug ID: 1507111973
IP: DisplayPort

What is the adaptive synchronization feature support plan for the DisplayPort Intel® FPGA IP core ?

Description

Below is the Adaptive Synchronization feature support plan by Intel® Quartus® Prime Pro Edition software and Standard Edition software.

1. For DisplayPort Source implementation, refer to the DisplayPort Intel® FPGA user guide documentation, Video Input Feature Comparisons table to enable adaptive synchronization feature.

2. For DisplayPort Sink implementation, refer to the Design Example Variant table and the Intel® Stratix® 10 DisplayPort SST Parallel Loopback with AdaptiveSync Support section in DisplayPort Intel® Stratix® 10 FPGA IP Design Example User Guide to enable adaptive sync feature in DPCD register.

 

 

Workaround/Fix

Refer to the table below for the DisplayPort Intel® FPGA IP core Adaptive Synchronization support plan.

FPGA Device Family Intel® Quartus® Prime Edition Software Adaptive Sync Support
Intel® Stratix® 10 (L-Tile and H-Tile) Pro Yes
Intel® Arria® 10 Pro Yes
Standard No
Intel® Cyclone® 10 GX Pro Yes
Standard No
Intel® Stratix® V Standard No
Intel® Arria® V Standard No
Intel® Cyclone® V Standard No