Device Family: Intel® Stratix® 10, Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 PX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX

Intel Software: Quartus Prime Pro

Type: Errata

Area: Intellectual Property


Last Modified: July 17, 2019
Version Found: v18.1
Bug ID: 1409077967

Riviera* Simulation Errors of the Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

Description

Due to a problem wih the ALDEC* Riviera* simulation tool, the following or similar error will be seen when simulating the Intel® Stratix® 10 Avalon®-ST and Single Root I/O Virtualization (SRIOV) Interface for PCI Express* Solutions IP.

ALOG: Error: VCP2950 SEG_WIDTH*2 is not a valid right-side of defparam.

Workaround/Fix

No workaround is available when using the ALDEC* Riviera* simulation tool. This problem is not seen with other supported simulators.

This problem has been reported to ALDEC*, a fix is scheduled for a future release of the ALDEC* Riviera* simulation tool.