Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: Wed Feb 06 2019 14:59:00 GMT-0800
Version Found: v18.1
Bug ID: 1408469747
IP: Altera PHYLite for Parallel Interfaces

Internal Error: Sub-system: CONSTRA, File: /quartus/db/constra/constra_runtime_rbc_checker.cpp, Line: 185

Description

Due to a problem in the Intel® Quartus® Prime Pro Edition software, you will get the above error message when setting a negative phase shift on the output clock in the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.

Workaround/Fix

To work around the problem, only set positive phase shift for any output clocks inside the PHY Lite for Parallel Interfaces Intel® Stratix® 10 FPGA IP.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition software.