Due to missing information, in the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide, the user guide does not include the procedure on how to access PMA register when the "Enable auto adaptation triggering for RX PMA CTLE/DFE mode" parameter is turned on.
In Intel® Quartus® Prime Pro Edition software version 19.2 onwards, a new register is introduced as stated below:
|0x343||PHY_TLKIT_ACCESS||With parameter Enable auto adaptation trigerring for RX PMA CTLE/DFE mode enabled, write 1’b1 to this register to hold the auto adaptation module FSM to an idle state.||31'hX1'b0||RW|
For Intel® Stratix® 10 H-tile production devices, disable the background calibration prior to access the transceiver core reconfiguration register. The Intel Stratix 10 H-tile ES devices and all variants of Intel® Stratix® 10 L-tile devices (ES and production) do not have background calibration.