Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: August 19, 2019
Version Found: v19.2
Bug ID: 1507317913

How to access the PMA register in the 25G Ethernet Intel® Stratix® 10 FPGA IP when "Enable auto adaptation triggering for RX PMA CTLE/DFE mode" parameter is turned on?

Description

Due to missing information, in the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide, the user guide does not include the procedure on how to access PMA register when the "Enable auto adaptation triggering for RX PMA CTLE/DFE mode" parameter is turned on.

In Intel® Quartus® Prime Pro Edition software version 19.2 onwards, a new register is introduced as stated below:

Addr Name Description Reset Access
0x343 PHY_TLKIT_ACCESS With parameter Enable auto adaptation trigerring for RX PMA CTLE/DFE mode enabled, write 1’b1 to this register to hold the auto adaptation module FSM to an idle state. 31'hX1'b0 RW

 

For Intel® Stratix® 10 H-tile production devices, disable the background calibration prior to access the transceiver core reconfiguration register. The Intel Stratix 10 H-tile ES devices and all variants of Intel® Stratix® 10 L-tile devices (ES and production) do not have background calibration. 

Workaround/Fix

To work around this problem in the Intel® Quartus® Prime Pro Edition software version 19.2 onwards, follow the steps below to access the transceiver core reconfiguration registers.

  1. Write 0x1 to register address 0x343 of the IP core Avalon® Memory Mapped control and status interface to hold the auto adaptation modulein an idle state. If you have disabled parameter "Enable auto adaptation triggering for RX PMA CTLE/DFE mode", you may skip this step.
  2. Write 0x0 into register 0x542[0] of the transceiver control and status registers using the transceiver reconfiguration Avalon Memory Mapped interface to disable background calibration.
  3. Access the transceiver register, for example, to perform the transceiver reconfiguration.
  4. Once completed, write 0x1 into register 0x542[0] of the transceiver control and status registers using the transceiver reconfiguration Avalon Memory Mapped interface to enable background calibration.
  5. Write 0x0 to register address 0x343 of the IP core Avalon Memory Mapped control and status interface to release the auto adaptation module. If you have disabled parameter "Enable auto adaptation triggering for RX PMA CTLE/DFE mode", you may skip this step.            

The detail above is scheduled to be added to a future release of the 25G Ethernet Intel® Stratix® 10 FPGA IP User Guide.