Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime

Type: Answers, Errata

Area: Intellectual Property


Last Modified: Thu Mar 21 2019 16:45:00 GMT-0700
Version Found: v18.1
Bug ID: 2206392639

How do I provide the Advance Interface Bus (AIB) clock to the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP using an IOPLL or a Native PHY in PLL Mode?

Description

Due to a restriction in the current release of the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP, external clock source cannot be used as an input to provide to the AIB clock.

Workaround/Fix

This capability is scheduled to be added to a future release of the Intel® Quartus® Prime software.