Due to a restriction in the current release of the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP, external clock source cannot be used as an input to provide to the AIB clock.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime
Type: Answers, Errata
Area: Intellectual Property
Last Modified: Thu Mar 21 2019 16:45:00 GMT-0700
Version Found: v18.1
Bug ID: 2206392639