Due to a problem in the Intel® Stratix® 10 Avalon® -ST Hard IP for PCIe* Design Example version 18.1 , you may observe this error when the "Generate HDL format" option is set to VHDL.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Type: Answers
Area: Intellectual Property
Last Modified: June 24, 2019
Version Found: v18.1
Version Fixed: v19.1
Bug ID: 2205695476
Error(16186): Can't elaborate top-level user hierarchy: "VHDL info at pcie_example_design.vhd(1337): back to vhdl to continue elaboration"
Description
Workaround/Fix
To work around this problem in the Intel® Quartus® Prime Pro Edition software version 18.1 set the "Generate HDL format" option to Verilog. This problem has been fixed beginning with the Intel® Quartus® Prime Pro Edition software version 19.1