You may see the above Critical Warning message or similar in Intel® Quartus® Prime Pro Edition software versions 19.3 and earlier when compiling a design targeting an industrial grade Intel® Stratix® 10 device which instances the JESD204B Intel FPGA IP or JESD204C Intel FPGA IP. This is because these IP only use two registers in a synchronizer chain which might have an unsafe Mean Time between Failure (MTBF) when it follows an asynchronous transfer. The recommended metastability synchronizer chain length for Intel® Stratix® 10 devices is three.
Device Family: Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Area: Intellectual Property
Last Modified: November 04, 2019
Version Found: v17.0
Bug ID: 1507420598,1507499722