Device Family: Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Intel® Cyclone® 10 GX, Intel® Cyclone® 10 LP, Intel® Stratix® 10 DX, Intel® Stratix® 10 GX, Intel® Stratix® 10 MX, Intel® Stratix® 10 PX, Intel® Stratix® 10 SX, Intel® Stratix® 10 TX
Intel Software: Quartus Prime Pro
Type: Answers, How-To
Area: Intellectual Property
Due to a problem with the Intel® Quartus® Prime Pro version 19.1, you may encounter the above critical warning when using the Triple-Speed Ethernet Intel® FPGA IP with LVDS I/O design when the default input termination
of LVDS reference clock is overridden by using the following QSF assignment or through the assignment editor.
set_instance_assignment -name INPUT_TERMINATION OFF -to ref_clk
To work around this problem, remove the following line from the QIP file of the Triple-Speed Ethernet Intel® FPGA IP when there is a need to override the default input termination of LVDS reference clock setting.
set_instance_assignment -entity "" -library "altera_lvds_core14_191" -name INPUT_TERMINATION DIFFERENTIAL -to inclock