Due to a problem with the 25G Ethernet Intel® FPGA IP v18.0 and earlier version, Intel® Quartus® Prime design compilation will show the warning message: "Ignored set_max_skew at alt_e2550_ptp_fifo_top.sdc" when implemented in VHDL and with multiple instances of the 25G Ethernet Intel FPGA IP in the design.
Device Family: Intel® Arria® 10, Intel® Stratix® 10
Intel Software: Quartus Prime Pro
Type: Errata
Area: Intellectual Property
Last Modified: August 15, 2018
Version Found: v17.1
Version Fixed: v18.0 Update 1
Bug ID: FB: 566816;
Why does the Intel® Quartus® Prime Pro compilation show warning message: "Ignored set_max_skew at alt_e2550_ptp_fifo_top.sdc" when compiling FPGA design with 25G Ethernet Intel® FPGA IP ?
Description
Workaround/Fix
To work around this problem:
In the file alt_e2550_ptp_fifo_top.sdc change:
FROM:
set inst_list [query_collection -list -all $inst]
foreach each_inst $inst_list {
TO:
foreach_in_collection each_inst_tmp $inst {
set each_inst [get_node_info -name $each_inst_tmp]
This problem has been fixed starting with Intel® Quartus® Prime Pro version 18.0.1