Device Family: Arria®, Intel® Arria® 10, Arria® II, Arria® V, Intel® Cyclone® 10 GX, Cyclone® IV GX, Cyclone® V GT, Cyclone® V GX, Cyclone® V ST, Cyclone® V SX, Intel® Stratix® 10, Stratix® II GX, Stratix® IV GT, Stratix® IV GX, Stratix® V GS, Stratix® V GT, Stratix® V GX, Stratix® GX

Type: Answers

Area: Intellectual Property

Last Modified: June 15, 2018

Why might my Intel® FPGA PCIe* IP fail to link train in some systems?


The PCIe* Card Present signals (PRSNT1_N, PRSNT2_N_X1, PRSNT2_N_X4, PRSNT2_N_X8, PRSNT2_N_X16) need to be correctly set in some smart host systems or the PCIe* Link may not train correctly.

For example some systems only attempt link training to the number of lanes indicated by the present signals for that slot. So if none of the present signals are enabled, the card may not train at all, or if for example only the x1 present signal is enabled, then a x4, x8 or x16 implementation may only train as a x1 interface configuration.


This problem is host system and BIOS dependent. Some systems ignore these signals. Ensure that the PRSNT signals are correclty enabled for you hardware, when using Intel® FPGA Development Kits, the PRSNT signals are typically selectable using a DIP switch.