Device Family: Intel® Arria® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: June 29, 2018
Bug ID: FB: 506044;

When using the Intel® Arria® 10 PCI* Express Hard IP, why are message data allocated vectors(0x05c) not writeable in the MSI capability structure when multiple message enable is set?

Description

In Intel® Arria® 10 FPGAs, the PCIe* message data allocated vector bits are not writeable when multiple message enable is set.

For example, when multiple message enable is set to 3'b010, and  32'hFFFFFFFF is written into configuration space Message Data Field, and user interrupt inputs are all 0, then software can only read 32'hFFFFFFFC.

This is a minor bug since the MSI packet generated by Intel® Arria® 10 Had IP is still correct.

Workaround/Fix

There is no plan to fix this problem. Your design must be aware that message data allocated vector bits are not always readable by SW when multiple message enable are set.