Due to a problem with the code generation for the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP version 18.0 an incorrect connection is made in the file alt_ehipc3_sl_soft.sv for the reset controller.
Device Family: Intel® Stratix® 10 TX
Intel Software: Quartus Prime Pro
Area: Intellectual Property
Last Modified: September 27, 2018
Version Found: v18.0
Version Fixed: v18.0 Update 1
Bug ID: FB: 557102;