Due to a problem in the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GE/25GE Example Design, the ethernet circuit is held in reset at startup and the link will not come up.
Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX
Area: Intellectual Property
Last Modified: January 07, 2019
Version Found: v18.1
Bug ID: FB: 2206133775;