Device Family: Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Answers

Area: Intellectual Property

Last Modified: January 07, 2019
Version Found: v18.1
Bug ID: FB: 2206133775;
IP: 25G Ethernet

Why is the E-Tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GE/25GE Design Example Held in Reset?


Due to a problem in the E-tile Hard IP for Ethernet Intel® Stratix® 10 FPGA IP 10GE/25GE Example Design, the ethernet circuit is held in reset at startup and the link will not come up.


To work around this problem, manually disable the reset by opening the example design in-system sources and probes and set source bits [3:1] to 3'b111.

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime Pro Edition.