Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property

IP: Avalon-ST Stratix 10 Hard IP for PCI Express, Avalon-MM Stratix 10 Hard IP for PCI Express

Why is my Intel® Stratix®10 GX ES device with PCIe* Hard IP unable to transmit TLP packets or show lowered bandwidth?


The Intel® Stratix®10 ES PCIe* Hard IP may encounter credit leakage  during TLP transmission.  When the Hard IP internal TX FIFO fills up, it may result in credit leakage. This may lead to the user interface getting throttled in conjunction with inaccurate credit consumed information being reported on the TX credit interface.
All Gen1, Gen2, and Gen3 configurations on Intel Stratix 10 GX devices with ES1 L-Tiles, ES2 L-Tiles or ES1 H-Tiles are impacted and may observe performance degradation resulting in lowered bandwidth.


To work around this errata, you must monitor and guard band the available credit for each transaction type: posted (P), non-posted (NP), and completion (Cpl) using the below formula. Do not calculate the tx_*_cdts_limit using the tx_*_cdts_consumed signal on the TX credit interface :
Available credit = Advertised credits from partner – GB
Where GB = 128 credits for data, 64 credits for header.
For devices that advertise less than 128 credits, this workaround does not apply.

Below is an example pseudo-code for NPH TLP traffic type (memory read without payload) to avoid credit leakage while it follows PCIe* ordering rule
1a.  Track the number of outstanding NP TLPs as follows

If (num_of_outstanding_NP_TLP < Initial_NPH_Credit) {

1b.  (OR) Guard band the available credit for the NPH TLPs as follows

If ((tx_nph_cdts – 64) > 0) {

This errata is fixed in Intel Stratix 10 GX devices with ES3 L-Tiles, Production L-Tiles, ES2 H-Tiles, or Production H-Tiles, and all Intel Stratix 10 SX devices.