Device Family: Intel® Arria® 10, Arria® V, Intel® Cyclone® 10, Stratix® V

Type: Answers

Area: Intellectual Property

Last Modified: February 09, 2018
Version Found: v17.1
Bug ID: FB: 314842;
IP: Altera Advanced SEU Detection

Advanced SEU Detection and Fault Injection IPs


Due to a problem with the Intel® Quartus® Prime software, you may see Timing Analyzer warnings regarding clocks with no constraints.

Timing constraints are required for proper operation of the SEU IPs (the Advanced SEU Detection and Fault Injection IPs). The user must provide these constraints in a Synopsys* Design Constraint (.sdc) file.


To work around this problem, add these constraints either by adding them directly into an existing SDC constraints file, or putting them into a separate file (for example, “seu_constraints.sdc”)


# constraints for SEU IP

create_clock -name intosc -period 10.000 [get_nets {*|alt_fault_injection_component|alt_fi_inst|intosc}]

create_generated_clock -name emr_unloader_STATE_CLOCKHIGH -source [get_nets {*|alt_fi_inst|intosc}] [get_keepers {*altera_emr_unloader:emr_unloader_component|current_state.STATE_CLOCKHIGH}]

create_generated_clock -name asd_current_state_MISS       -source [get_nets {*|alt_fi_inst|intosc}] [get_keepers {*|asd_cache:asd_cache_inst|current_state.STATE_MISS}]

create_generated_clock -name asd_cpuread_oneshot          -source [get_nets {*|alt_fi_inst|intosc}] [get_keepers {*|asd_cache:asd_cache_inst|asd_ext_oneshot:cpuread_oneshot|last}]


set_clock_groups -exclusive -group [get_clocks {emr_unloader_STATE_CLOCKHIGH}]

set_clock_groups -exclusive -group [get_clocks {asd_current_state_MISS}]

set_clock_groups -exclusive -group [get_clocks {asd_cpuread_oneshot}] 


This problem is not scheduled to be fixed in a future Intel® Quartus® Prime Software release.