Device Family: Intel® Arria® 10, Intel® Cyclone® 10, Intel® Stratix® 10, Stratix® V

Type: Answers, Errata

Area: Intellectual Property


Last Modified: August 15, 2018
Version Found: v13.1
Version Fixed: v18.1
Bug ID: FB: 567665;

Why is the Intel® FPGA Low Latency Ethernet 10G MAC IP not able to generate XON pause frames when priority flow control feature is enabled?

Description

Due to a problem with the Low Latency Ethernet 10G MAC Intel® FPGA IP, XON pause frames generation may not work for multiple queues if XOFF pause frame generation for multiple queues are enabled, followed by a XON pause frame generation for a single queue.

Workaround/Fix

There is no workaround for this problem.

This problem has been fixed starting in version 18.1 of the Intel® Quartus® Prime software.