Article ID: 000075718 Content Type: Troubleshooting Last Reviewed: 08/15/2018

Why is the Intel® FPGA Low Latency Ethernet 10G MAC IP not able to generate XON pause frames when priority flow control feature is enabled?

Environment

  • Intel® Quartus® Prime Pro Edition
  • Low Latency Ethernet 10G MAC Intel® FPGA IP
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    Critical Issue

    Description

    Due to a problem with the Low Latency Ethernet 10G MAC Intel® FPGA IP, XON pause frames generation may not work for multiple queues if XOFF pause frame generation for multiple queues are enabled, followed by a XON pause frame generation for a single queue.

    Resolution

    There is no workaround for this problem.

    This problem has been fixed starting in version 18.1 of the Intel® Quartus® Prime software.

    Related Products

    This article applies to 4 products

    Intel® Arria® 10 FPGAs and SoC FPGAs
    Stratix® V FPGAs
    Intel® Cyclone® 10 FPGAs
    Intel® Stratix® 10 FPGAs and SoC FPGAs

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