Device Family: Intel® Stratix® 10

Type: Answers, Errata

Area: Intellectual Property


Last Modified: June 25, 2018
Version Found: v18.0 Update 1
Bug ID: FB: 570720;
IP: Interlaken IP Core (2nd Generation)

Why are the transceivers not reset correctly when using the Interlaken (2nd Generation) Intel® FPGA IP on Intel® Stratix® 10 FPGA?

Description

Due to a problem in the Intel® Quartus® Prime software version 18.0 and earlier, asserting the reset_n signal on the Interlaken (2nd Generation) Intel FPGA IP will not reset the transceivers contained within the core. 

Workaround/Fix

To work around this problem, manually connect the reset_n signal within the cleartext wrapper ilk_uflex_ext module contained in the IP core as shown below:

Original Code:

uflex_ilk_hard_pcs_xcvr #(

    .NUM_LANES (NUM_LANES),

    ...

    )C2_XCVR(

    //reset controller

    .mm_clk (mm_clk), //75-125 MHz

    .reset_n,

    ...

Workaround Code:

    ...

    ) C2_xcvr (

    //reset controller

    .mm_clk (mm_clk), //75-125 MHz

    .reset_n (reset_n),

    ...

This problem is scheduled to be fixed in a future release of the Intel® Quartus® Prime software.