Due to a problem in the Intel® Quartus® Prime software version 18.0 and earlier, asserting the reset_n signal on the Interlaken (2nd Generation) Intel FPGA IP will not reset the transceivers contained within the core.
Device Family: Intel® Stratix® 10
Type: Answers, Errata
Area: Intellectual Property
Last Modified: June 25, 2018
Version Found: v18.0 Update 1
Bug ID: FB: 570720;
IP: Interlaken IP Core (2nd Generation)