Device Family: Intel® Arria® 10, Intel® Cyclone® 10, Intel® Stratix® 10

Type: Answers

Area: Intellectual Property

Last Modified: August 14, 2018
Version Found: v15.1
Bug ID: FB: 572448;

Why does the SYNC_N signal keep asserting when using the JESD204B IP Example Design in Intel® Stratix® 10, Intel® Arria® 10 or Intel® Cyclone® 10 GX devices?


Due to a problem in Intel® Quartus® Prime Standard/Prime Pro software version 18.0 and earlier, the SYNC_N signal may assert unexpectedly when using the JESD204B IP Example Design in Intel Stratix® 10, Intel Arria® 10 or Intel Cyclone® 10 GX devices.

This is because, in the JESD204B design example, the sysref signal is sampled through software (NIOS/System Console) in the mgmt_clk domain, which is asynchronous to the IP core domain link_clk. The IP core operation is rising edge sensitive to sysref pulse. The asynchronous sysref signal may cause its rising edge to go undetected in the link_clk domain.


To work around this, synchronize the sysref signal to the link_clk domain in the top wrapper of the JESD204B IP example design. (altera_jesd204_ed_RX/TX/RX_TX).

This issue is schedued to be fixed in a future release of the Intel Quartus Prime Standard/Pro software.