Due to a problem in Intel® Quartus® Prime Standard/Prime Pro software version 18.0 and earlier, the SYNC_N signal may assert unexpectedly when using the JESD204B IP Example Design in Intel Stratix® 10, Intel Arria® 10 or Intel Cyclone® 10 GX devices.
This is because, in the JESD204B design example, the sysref signal is sampled through software (NIOS/System Console) in the mgmt_clk domain, which is asynchronous to the IP core domain link_clk. The IP core operation is rising edge sensitive to sysref pulse. The asynchronous sysref signal may cause its rising edge to go undetected in the link_clk domain.