Device Family: Cyclone® V

Type: Answers, How-To

Area: Intellectual Property

Version Found: v16.1
Bug ID: FB: 530556;
IP: Cyclone V Hard IP for PCI Express

Why does the serdes_pll_locked signal of upper PCI* Express Hard IP of Intel® Cyclone® V devices does not lock?


Due to a problem with Intel® Quartus® prime software, Intel® Cyclone® V device that include 6 transceiver channels and two PCIe* Hard IPs will see a problem where the upper PCIe* Hard IP's serdes_pll_locked signal is unable to lock. The lower PCIe Hard IP does not has this issue and is working correctly.


To work around this problem, run the enable_rx_pma_direct.xml script on top of Quartus generated SOF file. 

Run the script from the command line as shown below, download the .xml script from here and run it from the same directory as Quartus project file (.qpf).

quartus_asm -e <name_of_sof> -x enable_rx_pma_direct.xml

This problem will not be fixed in a future release of the Intel® Quartus® Prime software.