Device Family: Intel® Arria® 10, Arria® V, Intel® Stratix® 10

Type: Answers, How-To

Area: Intellectual Property


Version Found: v17.1
Bug ID: FB: 537354;

Why does the rx_digitalreset and tx_digitalreset signals of 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP core cannot connect to the Transceiver PHY reset controller Intel® FPGA IP in Platform Designer?

Description

Due to a problem with Intel® Quartus® Prime software, the 1G/2.5G/5G/10G Multi-rate Ethernet PHY Intel® FPGA IP has incorrect type of interface for rx_digitalreset and tx_digitalreset signals, therefore you cannot connect these two signals to the Transceiver PHY reset controller Intel FPGA IP at Platform Designer. The correct type of interface for rx_digitalreset and tx_digitalreset signals are conduit NOT reset.

Workaround/Fix

Export the rx_digitalreset and tx_digitalreset signals from Platfrom Designer and manually connect at RTL. This problem will be fixed in a future version of Intel Quartus Prime software.