Device Family: Intel® Stratix® 10 TX

Type: Answers, Errata

Area: Intellectual Property


Last Modified: September 25, 2018
Version Found: v18.0
Version Fixed: v18.1
Bug ID: FB: 587832;

When using the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, why are the o_clk_rec_div66 and o_clk_pll_div66 clock rates reported incorrectly during timing analysis?

Description

Due to a problem with Intel® Quartus® Prime software Pro version 18.0.1 and earlier, the output clock frequency of the E-tile Hard IP for Ethernet Intel® FPGA IP in 10G/25G mode, signals o_clk_rec_div66 and o_clk_pll_div66 is reported incorrectly in timing analysis. The correct frequency for o_clk_rec_div66 is 156.25MHz and o_clk_pll_div66 is 390.625MHz.

Workaround/Fix

No workaround for this problem is available.

This problem has been fixed starting in Intel® Quartus® Prime Pro software version 18.1.