Why does the Low Latency Ethernet 10G MAC's dynamic generated example design has incorrect accuracy of 1588 latency figure?

To work around this problem:

1. For Intel Quartus Prime v16.0, after generated the affected example design, open altera_eth_multi_channel_1588.sv file from this directory  "<project_directory>\rtl" and modify the following lines to the correct figure as below: 

localparam  DEFAULT_NSEC_PERIOD_10G     = 4'h3;                     

           localparam  DEFAULT_FNSEC_PERIOD_10G    = 16'h3333; 

2. For Intel Quartus Prime v16.1 and above, after generated the affected example design, from Intel Quartus Prime menu, click “Open” and navigate to "<project_directory>\rtl\altera_eth_1588_tod" and select altera_eth_1588_tod_10g.ip to launch the IP Parameter Editor of Intel 10G 1588 Time-of-day module, and then update the following parameters to the correct figure as below:

           DEFAULT_NSEC_PERIOD to 3

           DEFAULT_FNSEC_PERIOD to 0x00003333

           DEFAULT_NSEC_ADJPERIOD to 3

           DEFAULT_FNSEC_ADJPERIOD to 0x00003333

This problem is scheduled to be fixed in a future version of the Intel Quartus Prime software.