Device Family: Intel® Arria® 10, Intel® Cyclone® 10 GX, Intel® Stratix® 10

Type: Errata

Area: Intellectual Property


Last Modified: August 22, 2018
Version Found: v18.0
Bug ID: FB: 587132;

Why does the Low Latency Ethernet 10G MAC Intel® FPGA IP ignore sequential XON requests when implemented with Priority-based Flow Control (PFC) queues?

Description

Due to a problem with the Intel® Quartus® Prime software version 18.0.1 and earlier, the Low Latency Ethernet 10G MAC Intel® FPGA IP only accepts the first XON request when implemented with Priority-Based Flow Control (PFC) queues. All subsequent XON requests will be ignored and the remaining paused queues will stay paused until the pause quanta expire or become zero.

Workaround/Fix

To work around this problem, have all the paused queues resume simultaneously through a single XON or wait for the pause quanta expiry for the remaining paused priority queues.

This problem is scheduled to be fixed in a future version of the Intel Quartus Prime software.