Device Family: Intel® Stratix® 10, Intel® Stratix® 10 MX, Intel® Stratix® 10 TX

Type: Answers, Errata

Area: Intellectual Property


Last Modified: May 10, 2018
Version Found: v18.0
Bug ID: FB: 555284;

Why does the Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP core forward RX truncated invalid frames to user logic?

Description

The v18.0 Intel® Stratix® 10 E-tile Hard IP for Ethernet Intel FPGA IP core has a problem with oversized frame stripping.

When the RX MAC receives a frame size >= 65536, and enforce_max_frame_size is enabled, the frame output from RX MAC to user logic will be truncated to frame size specified by max_rx_frame_size settings, and a second invalid frame will output from the RX MAC to user logic starting from 65536-byte to the end of the super large frame.

Workaround/Fix

No workaround to this problem currently exists.

This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime software.