According to the PCIe* spec, when a PCIe* physical layer receives nullified TLPs (including posted and non-posted TLPs), it should discard the nullified TLPs and free any storage allocated for these TLPs. Due to a problem with the Intel® Arria® 10 PCIe* Hard IP, when it receives nullified TLPs, it treats them as correctable error and sets the correctable error register.
Device Family: Intel® Arria® 10, Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Intel® Cyclone® 10 GX
Type: Answers, Errata
Area: Intellectual Property
Last Modified: August 14, 2018
Version Found: v18.0
Bug ID: FB: 571646;
IP: Arria 10 Hard IP for PCI Express