Device Family: Intel® Arria® 10, Intel® Arria® 10 GT, Intel® Arria® 10 GX, Intel® Arria® 10 SX, Intel® Cyclone® 10 GX

Type: Answers, Errata

Area: Intellectual Property


Last Modified: August 14, 2018
Version Found: v18.0
Bug ID: FB: 571646;

Why does the Intel® Arria® 10 PCIe* Hard IP treat nullified TLPs (including posted TLPs and non-posted TLPs) as correctable error and set the correctable error register?

Description

According to the PCIe* spec, when a PCIe* physical layer receives nullified TLPs (including posted and non-posted TLPs), it should discard the nullified TLPs and free any storage allocated for these TLPs. Due to a problem with the Intel® Arria® 10 PCIe* Hard IP, when it receives nullified TLPs, it treats them as correctable error and sets the correctable error register.

Workaround/Fix

No workaround for this problem exists. The user application should be aware of the limitation and take care of this scenarios. If correctable errors are reported by the Intel® Arria® 10 PCIe* Hard IP, the user application can ignore these if they are caused by nullified packets. Typically nullified packets are only utilized in PCIe* Switch applications.

This problem will not be fixed in a future release of the Intel® Quartus® Prime software.