Device Family: Intel® Stratix® 10

Intel Software: Quartus Prime Pro

Type: Answers

Area: Intellectual Property


Last Modified: December 18, 2018
Version Found: v18.1
Bug ID: FB: 2007757464 / 1408300138;
IP: High-Speed Reed-Solomon

Why does the High Speed Intel® Reed Solomon FPGA IP Core generate an incorrect set of check symbols for my data?

Description

Due to a problem with the RTL source generation of the High Speed Intel® Reed Solomon FPGA IP Core, if the 'Hyper-optimization' parameter is set to 'High' the IP will generate an incorrect set of check symbols for the incoming data payload.
 

Workaround/Fix

To work around this problem, set the 'Hyper-optimization' parameter to 'Low'.

This problem is schedule to be fixed on a future release of the High Speed Intel® Reed Solomon FPGA IP Core.