Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: March 26, 2018
Version Found: v17.1 Update 1
Bug ID: FB: 535256;

Why does the generated Intel® Stratix® 10 100G Ethernet soft IP with RS-FEC example design fail to complete simulation?

Description

Due to a problem in the simulation testbench of the example design generated by the Intel® Quartus® Prime Pro software version 17.1.1, the simulation fails to complete.  You will see the simulation hang at packet 10 as shown below.

 

***************************************************

**************   Recieve Ready   ******************

***************************************************

Transmitting test data

** Sending Packet           1...

** Sending Packet           2...

** Sending Packet           3...

** Sending Packet           4...

** Sending Packet           5...

** Sending Packet           6...

** Sending Packet           7...

** Sending Packet           8...

** Sending Packet           9...

** Sending Packet          10...

Workaround/Fix

To work around this problem, replace the original generated testbench <your example project>/example_testbench/basic_avl_tb_top.v with this new testbench.

This problem is scheduled to be fixed in a future version of the Intel® Quartus® Prime Pro software.