Device Family: Arria® II, Arria® V, Cyclone® IV, Cyclone® V, Stratix® IV, Stratix® V

Type: Answers

Area: Intellectual Property

Last Modified: December 05, 2018
Version Found: v17.1
Bug ID: FB: 585764;

Why does the Ethernet 10G MAC Intel® FPGA IP's XGMII interface output last few bytes of data with unknown state in simulation?


You may encounter above problem if the csr_reset signal of Ethernet 10G MAC Intel® FPGA IP did not toggle once after the start of simulation.


To work around this problem, the csr_reset signal needs to be toggled once at the beginning of simulation.