Device Family: Intel® Stratix® 10

Type: Answers

Area: Intellectual Property


Last Modified: April 16, 2018
Version Found: v18.0
Version Fixed: v18.0 Update 1
Bug ID: FB: 551763;

Why does Stratix 10 HDMI design example Rx lock time is longer ?

Description

Due to a problem with the Stratix® 10 HDMI IP in Quartus® Prime Pro edition version 18.0, user may observe HDMI Rx takes longer time to lock for HDMI 2.0 resolution as compared to Arria® 10 HDMI IP Design Example.

This is due to the change of the behavior in the rx_std_bitslipboundary_sel of Synchronous State Machine Word Alignment in Stratix 10 FPGA that incur additional delay causing HDMI IP Rx harder to achieve fast alignment.

Workaround/Fix

There is no workaround.

This problem is fixed in Quartus® Prime Pro version 18.0 update 1.